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oki semiconductor feds5412222b-01 issue date: nov.,20, 2002 msm5412222b 262,214-word 12-bit field memory 1/17 general description the oki msm5412222b is a high performance 3-mbit, 256k 12-bit, field memory. it is especially designed for high-speed serial access applications such as hdtv s, conventional ntsc tvs, vtrs, digital movies and multi-media systems. msm5412222b is a fram for wide or low end use in general commodity tvs and vtrs exclusively. msm5412222b is not designed for the other use or high end use in medical systems, professional graphics systems which require long term pict ure storage, data storage systems and others. more than two msm5412222bs can be cascaded directly without any delay devices among the msm5412222bs. (cascading of msm5412222b provides larger storage depth or a longer delay). each of the 12-bit planes has separate serial write and read ports. these employ independent control clocks to support asynchronous read and write op erations. different clock rates are also supported that allow alternate data rates between write and read data streams. the msm5412222b provides high speed fifo, first-in first-out, operation without external refreshing: msm5412222b refreshes its dram storage cells automatically, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refr eshing operations are preven ted by special arbitration logic. the msm5412222b?s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. the delay length, number of read delay cl ocks between write and read, is determined by externally controlled write and read reset timings. additional sram serial registers, or line buffers for the initial access of 256 12-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. additionally, the msm5412222b has write mask function or input enable function (ie), and read-data skipping function or output enable function (oe) . the differences between write enable (we) and input enable (ie), and between read enable (re) and output enable (oe) ar e that we and re can stop serial write/read address increments, but ie and oe cannot stop the increment, when write/read clocking is continuously applied to msm5412222b. the input enable (ie) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. this facilitates data processing to display a ?picture in picture? on a tv screen. the msm5412222b is similar in operation and functionality to oki 1-mbit field memory msm514222c and 2-mbit field memory msm518222a. three msm514222cs or one msm514222c plus one msm518222a can be replaced simply by one msm5412222b.
feds5412222b-01 oki semiconductor msm5412222b 2/17 features ? single power supply: 5.0 v 0.5 v ? 262,214 words 12 bits ? fast fifo (first-in first-out) operation ? high speed asynchronous serial access read/write cycle time 25 ns/30 ns access time 23 ns/25 ns ? direct cascading capability ? write mask function (input enable control) ? data skipping function (output enable control) ? self refresh (no refresh control is required) ? package options: 44-pin 400 mil plastic tsop (type 2) (tsop(2)44-p-400-0.80-k) (product:MSM5412222B-XXTS-K) 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product: msm5412222b-xxjs) xx indicates speed rank. product family family access time (max.) cycle time (min.) package msm5412222b-25ts-k 23 ns 25 ns msm5412222b-30ts-k 25 ns 30 ns 400 mil 44-pin tsop (2) msm5412222b-25js 23 ns 25 ns msm5412222b-30js 25 ns 30 ns 400 mil 40-pin soj
feds5412222b-01 oki semiconductor msm5412222b 3/17 pin configuration (top view) pin name function swck serial write clock srck serial read clock we write enable re read enable ie input enable oe output enable rstw write reset clock rstr read reset clock d in 0 to 11 data input d out 0 to 11 data output v cc power supply (5.0 v) v ss ground (0 v) nc no connection note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. v ss v cc d out 11 d out 10 d out 9 d out 8 d out 7 d out 6 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 srck rstr re oe v ss v cc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v ss nc d in 11 d in 10 d in 9 d in 8 d in 7 d in 6 d in 5 d in 4 d in 3 d in 2 d in 1 d in 0 swc k rstw we ie nc v cc v ss d out 11 d out 10 nc d out 9 d out 8 d out 7 d out 6 v cc d out 5 d out 4 d out 3 d out 2 v ss d out 1 d out 0 srck rstr nc re oe v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v ss d in 11 d in 10 nc d in 9 d in 8 d in 7 d in 6 nc d in 5 d in 4 d in 3 d in 2 nc d in 1 d in 0 swc k rstw nc we ie v cc 44-pin plastic tsop (2) (k type) 40-pin plastic soj
feds5412222b-01 oki semiconductor msm5412222b 4/17 block diagram clock oscillator x 262,144 12 memory array serial read re g ister ( 12 ) read line buffer write line buffer ( 12 ) serial read controller re rstr srck data-out buffer ( 12) d out ( 12) read/write and refresh controller sub-register ( 12) decoder oe ( 12) 71-word sub-register ( 12) serial write register ( 12) 71-word v bb generator we rstw swck data-in buffer ( 12) d in ( 12) ie serial write controller
feds5412222b-01 oki semiconductor msm5412222b 5/17 operation write operation the write operation is controlled by three clocks, swck, rstw, and we. write operation is accomplished by cycling swck, and holding we high after the write address pointer reset operation or rstw. each write operation, which begins after rstw, must cont ain at least 150 active write cycles, i.e. swck cycles while we is high. to transfer the last data to the dram array, which at that time is stored in the serial data registers attached to the dram array, an rstw operation is required after the last swck cycle. note that every write timing of msm5412222b is delayed by one clock compared with read timings for easy cascading without any interface delay devices. write reset: rstw the first positive transition of swck after rstw becomes high resets the write addre ss counters to zero. rstw setup and hold times are referenced to the rising edge of swck. because the write reset function is solely controlled by the swck rising edge after the high level of rstw, the states of we and ie are ignored in the write reset cycle. before rstw may be brought high again for a further reset operation, it must be low for at least two swck cycles. data inputs: d in 0 to 11 write clock: swck the swck latches the input data on chip when we is high , and also increments the internal write address pointer. data-in setup time t ds , and hold time t dh are referenced to the rising edge of swck. write enable: we we is used for data write enable/disable control. we hi gh level enables the input, and we low level disables the input and holds the internal write address pointer. there are no we disable time (low) and we enable time (high) restrictions, because the msm5412222b is in fully static ope ration as long as the power is on. note that we setup and hold times are referenced to the rising edge of swck. input enable: ie ie is used to enable/disable writing into memory. ie hi gh level enables writing. the in ternal write address pointer is always incremented by cycling swck regardless of the ie level. note that ie setup and hold times are referenced to the rising edge of swck.
feds5412222b-01 oki semiconductor msm5412222b 6/17 read operation the read operation is controlled by three clocks, srck, rstr, and re. read operation is accomplished by cycling srck, and holding re high after the r ead address pointer reset operation or rstr. each read operation, which begins after rstr, must contain at least 150 active read cycles, i.e. srck cycles while re is high. read reset: rstr the first positive transition of srck after rstr becomes high resets the read address counters to zero. rstr setup and hold times are referenced to the rising edge of srck. because the r ead reset function is solely controlled by the srck rising edge after the high level of rstr, the states of re and oe are ignored in the read reset cycle. before rstr may be brought high again for a further reset operation, it must be low for at least *two srck cycles. data out: d out 0 to 11 read clock: srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re is high during a read operation. the srck input increments the internal read address pointer when re is high. the three-state output buffer provides direct ttl compatibilit y (no pullup resistor required ). data out is the same polarity as data in. the output becomes valid after the access time interval t ac that begins with the rising edge of srck. *there are no output valid time restriction on msm5412222b. read enable: re the function of re is to gate of the srck clock for incr ementing the read pointer. wh en re is high before the rising edge of srck, the read pointer is incremented. wh en re is low, the read pointer is not incremented. re setup times (t rens and t rdss ) and re hold times (t renh and t rdsh ) are referenced to the rising edge of the srck clock. output enable: oe oe is used to enable/disable the outputs. oe high level enables the outputs. the intern al read address pointer is always incremented by cycling srck regardless of the oe le vel. note that oe setup and hold times are referenced to the rising edge of srck.
feds5412222b-01 oki semiconductor msm5412222b 7/17 power-up and initialization on power-up, the device is designed to begin proper operation after at least 100 s after v cc has stabilized to a value within the range of recommended operating conditions. after this 100 s stabilization interval, the following initialization sequence must be performed. because the read and write address counters are not valid after power-up, a mi nimum of 80 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw operation and an rstr operation, to properly initialize the write and the read addr ess pointer. dummy write cycles/rstw and dummy read cycles /rstr may occur simultaneously. if these dummy read and write operations start while v cc and/or the substrate voltage has not stabilized, it is necessary to perform an rstr operation plus a minimum of 80 srck cycles plus another rstr operation, and an rstw operation plus a minimum of 80 srck cycles plus another rstw operation to properly initialize read and write address pointers. old/new data access there must be a minimum delay of 150 swck cycles be tween writing into memory and reading out from memory. if reading from the first field starts w ith an rstr operation, before the star t of writing the second field (before the next rstw operation), then the data just written will be read out. the start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 20 swck cycles. if the rstr operatio n for the first field read-out occurs less than 20 swck cycles after the rstw operatio n for the second field write-in, then the in ternal buffering of the device assures that the first field will still be read out. the first field of data th at is read out while the second field of data is written is called ?old data?. in order to read out ?new data?, i.e., the second fiel d written in, the delay between an rstw operation and an rstr operation must be at least 150 srck cycles. if the delay between rstw and rstr operations is more than 21 but less than 150 cycles, then the data read out will be undetermined. it may be ?old data? or ?new? data, or a combination of old and new data. such a timing should be avoided. cascade operation the msm5412222b is designed to allow easy cascading of multiple memory devices. this provides higher storage depth, or a longer delay than can be achieved with only one memory device.
feds5412222b-01 oki semiconductor msm5412222b 8/17 electrical characteristics absolute maximum ratings parameter symbol conditon rating unit input output voltage v t at ta = 25 c, v ss ?1.0 to +7.0 v output current i os ta = 25 c 50 ma power dissipation p d ta = 25 c 1 w operating temperature t opr ? 0 to 70 c storage temperature t stg ? ?55 to +150 c recommended operating conditions parameter symbol min. typ max. unit power supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.4 v cc v cc +1 v input low voltage v il ?0.1 0 +0.8 v dc characteristics parameter symbol condition min. max. unit input leakage current i li 0 < v i < v cc + 1 v, other pins tested at v = 0 v ?10 +10 a output leakage current i lo 0 < v o < v cc ?10 +10 a output ?h? level voltage v oh i oh = ?1 ma 2.4 ? v output ?l? level voltage v ol i ol = 2 ma ? 0.4 v operating current i cc1 minimum cycle time, output open ? 60 ma standby current i cc2 input pin = v ih /v il ? 5 ma capacitance (ta = 25c, f = 1 mhz) parameter symbol max. unit input capacitance (d in , swck, srck, rstw, rstr, we, re, ie, oe) c i 6 pf output capacitance (d out ) c o 7 pf
feds5412222b-01 oki semiconductor msm5412222b 9/17 ac characteristics (v cc = 5.0 v 0.5 v, ta = 0 to 70c) msm5412222b-25 msm5412222b-30 parameter symbol min. max. min. max. unit access time from srck t ac ? 23 ? 25 ns d out hold time from srck t ddck 6 ? 6 ? ns d out enable time from srck t deck 6 23 6 25 ns swck ?h? pulse width t wswh 9 ? 12 ? ns swck ?l? pulse width t wswl 10 ? 12 ? ns input data setup time t ds 2 ? 2 ? ns input data hold time t dh 4 ? 4 ? ns we enable setup time t wens 0 ? 0 ? ns we enable hold time t wenh 3 ? 3 ? ns we disable setup time t wdss 0 ? 0 ? ns we disable hold time t wdsh 3 ? 3 ? ns ie enable setup time t iens 0 ? 0 ? ns ie enable hold time t ienh 3 ? 3 ? ns ie disable setup time t idss 0 ? 0 ? ns ie disable hold time t idsh 3 ? 3 ? ns we ?h? pulse width t wweh 5 ? 10 ? ns we ?l? pulse width t wwel 5 ? 10 ? ns ie ?h? pulse width t wieh 5 ? 10 ? ns ie ?l? pulse width t wiel 5 ? 10 ? ns rstw setup time t rstws 0 ? 0 ? ns rstw hold time t rstwh 3 ? 3 ? ns srck ?h? pulse width t wsrh 9 ? 12 ? ns srck ?l? pulse width t wsrl 10 ? 12 ? ns re enable setup time t rens 0 ? 0 ? ns re enable hold time t renh 3 ? 3 ? ns re disable setuptime t rdss 0 ? 0 ? ns re disable hold time t rdsh 3 ? 3 ? ns oe enable setup time t oens 0 ? 0 ? ns oe enable hold time t oenh 3 ? 3 ? ns oe disable setuptime t odss 0 ? 0 ? ns oe disable hold time t odsh 3 ? 3 ? ns output buffer turn-off de lay time from oe t oez 17 ? 17 ? ns re ?h? pulse width t wreh 5 ? 10 ? ns re ?l? pulse width t wrel 5 ? 10 ? ns oe ?h? pulse width t woeh 5 ? 10 ? ns oe ?l? pulse width t woel 5 ? 10 ? ns rstr setup time t rstrs 0 ? 0 ? ns rstr hold time t rstrh 3 ? 3 ? ns swck cycle time t swc 25 ? 30 ? ns srck cycle time t src 25 ? 30 ? ns transition time (rise and fall) t t 3 30 3 30 ns
feds5412222b-01 oki semiconductor msm5412222b 10/17 notes: 1. input signal reference levels for the parameter measurement are v ih = 3.0 v and v il = 0 v. the transition time t t is defined to be a transition time that signal transfers between v ih = 3.0 v and v il = 0 v. 2. ac measurements assume t t = 3 ns. 3. read address must have more than a 150 ad dress delay than write address in every cycle when asynchronous read/write is performed. 4. read must have more than a 150 address delay than write in order to read the data written in a current series of write cycles which has been st arted at last write reset cycle: this is called ?new data read?. when read has less than a 20 address delay t han write, the read data are the data written in a previous series of write cycles which had been wr itten before at last writ e reset cycle: this is called ?old data read?. 5. when the read address delay is between more than 21 and less than 149, read data will be undetermined. however, normal write is achieved in this address condition. 6. outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh = 2.0 v and v ol = 0.8 v.
feds5412222b-01 oki semiconductor msm5412222b 11/17 timing waveform write cycle timing (write reset) swck rstw d in we n ? 1 n 01 2 n cycle 0 cycle 1 cycle 2 cycle t t t rstws t rstwh t swc t ds t dh t wswh t wswl ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il ie ? v ih ? v il write cycle timing (write enable) swck we ie n ? 1 n cycle disable cycle disable cycle n + 1 cycle t wenh t wdss t wens t wwel t wweh t wdsh n + 1 ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il d in n rstw ? v ih ? v il
feds5412222b-01 oki semiconductor msm5412222b 12/17 write cycle timing (input enable) swck ie d in we n ? 1 n + 3 n cycle n + 1 cycle n + 2 cycle n + 3 cycle t ienh t idss t iens t wiel t wieh t idsh n rstw ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il read cycle timing (read reset) srck rstr d out re n ? 1 n 012 n cycle 0 cycle 1 cycle 2 cycle t t t rstrs t rstrh t src t ac t wsrh t wsrl oe t ddck ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v oh ? v ol
feds5412222b-01 oki semiconductor msm5412222b 13/17 read cycle timing (read enable) srck re oe n + 1 n cycle disable cycle disable cycle n + 1 cycle n rstr ? v ih ? v il ? v ih ? v il ? v ih ? v il ? v oh ? v ol ? v ih ? v il t renh t wrel t rdsh t rdss t wreh t rens d out n ? 1 read cycle timing (output enable) srck oe d out rstr n ? 1 n + 3 ? v ih n cycle n + 1 cycle n + 2 cycle n + 3 cycle t oenh t woel t odsh t odss t woeh n hi-z t deck t oens ? v il ? v ih ? v il ? v ih ? v il ? v oh ? v ol re ? v ih ? v il t oez
feds5412222b-01 oki semiconductor msm5412222b 14/17 package dimensions notes for mounting the surface mount type packages the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). tsop(2)44-p-400-0.80-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.54 typ. 5 rev. no./last revised 3/dec. 10, 1996 (unit: mm)
feds5412222b-01 oki semiconductor msm5412222b 15/17 notes for mounting the surface mount type packages the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact oki?s respons ible sales person for the product name, package name, pin number, package code a nd desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.70 typ. 5 rev. no./last revised 5/dec. 5, 1996 (unit: mm)
feds5412222b-01 oki semiconductor msm5412222b 16/17 revision history page document no. date previous edition current edition description feds5412222b-01 nov.,20 , 2002 ? ? final edition 1
feds5412222b-01 oki semiconductor msm5412222b 17/17 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improp er installation, repair, alteration or accident, improp er handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicati on equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and auto motive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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